Data Sheet
June 1999
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 54. Series 2 Readback Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C ≤ TA ≤ +85 °C.
Parameter
RD_CFGN to CCLK Setup Time
RD_CFGN High Width to Abort Readback
CCLK Low Time
Symbol
TS
Min
50
2
Max
—
Unit
ns
TRBA
TCL
—
CCLK
ns
50
50
—
—
—
CCLK High Time
TCH
FC
—
ns
CCLK Frequency
10
50
MHz
ns
CCLK to RD_DATA Delay
TD
TRBA
RD_CFGN
TCL
TS
CCLK
TCH
TD
RD_DATA
BIT 0
BIT 0
BIT 1
5-4536(F)
Figure 72. Readback Timing Diagram
Lucent Technologies Inc.
167
ETC [ ETC ]
