Data Sheet
June 1999
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 51A. OR2CxxA/OR2TxxA Synchronous Peripheral Configuration Mode Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
CCLK to DOUT
Symbol
TS
Min
20
0
Max
—
Unit
ns
TH
—
ns
TCH
TCL
FC
50
50
—
—
—
ns
—
ns
10
30
MHz
ns
TD
Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].
Table 51B. OR2TxxB Synchronous Peripheral Configuration Mode Timing Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
D[7:0] Setup Time
D[7:0] Hold Time
CCLK High Time
CCLK Low Time
CCLK Frequency
CCLK to DOUT
Symbol
TS
Min
15
Max
—
Unit
ns
TH
0
—
ns
TCH
TCL
FC
12.5
12.5
—
—
ns
—
ns
40
10
MHz
ns
TD
—
Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].
TCH
CCLK
TINIT_CLK
TCL
INIT
TH
TS
D[7:0]
BYTE 1
BYTE 0
TD
DOUT
RDY
0
1
2
3
4
5
6
7
0
5-4534(F)
Figure 69. Synchronous Peripheral Configuration Mode Timing Diagram
164
Lucent Technologies Inc.
ETC [ ETC ]
