FLEX 10KE Embedded Programmable Logic Family Data Sheet
For more information on FLEX device configuration, see the following
documents:
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Configuration Devices for APEX & FLEX Devices Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlaster Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
Application Note 116 (Configuring APEX 20K,FLEX 10K, and FLEX 6000
Devices)
FLEX 10KE devices are supported by the MAX+PLUS II development
system, which is an integrated package that offers schematic, text
(including AHDL), and waveform design entry, compilation and logic
synthesis, full simulation and worst-case timing analysis, and device
configuration. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0,
LPM, VHDL, Verilog HDL, and other interfaces for additional design
entry and simulation support from other industry-standard PC- and
UNIX workstation-based EDA tools.
The MAX+PLUS II software works easily with common gate array EDA
tools for synthesis and simulation. For example, the MAX+PLUS II
software can generate Verilog HDL files for simulation with tools such as
Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains
EDA libraries that use device-specific features such as carry chains, which
are used for fast counter and arithmetic functions. For instance, the
Synopsys Design Compiler library supplied with the MAX+PLUS II
development system includes DesignWare functions that are optimized
for the FLEX 10KE architecture.
The MAX+PLUS II development system runs on Windows-based PCs and
Sun SPARCstation, and HP 9000 Series 700/800, and IBM RISC
System/6000 workstations.
See the MAX+PLUS II Programmable Logic Development System & Software
Data Sheet for more information.
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Altera Corporation
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ETC [ ETC ]
