CY545 Stepper System Controller
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The read or write is broken into two steps. First the lower address byte is generated on the data
bus. This value is latched into the other 74LS373, using the ALE signal. Then the actual data
transfer occurs. For a write, the CY545 generates the write data on the data bus, along with a
write strobe, WR. For a read, the data bus is floated, and a read strobe is generated, using RD,
so the memory can now drive the bus.
When the memory transfer is over, the XMEM_SEL signal goes high again, de-selecting the
external memory. This allows the lower address byte and RD and WR strobes to be used with
other hardware as well, without interference from the memory. Only the memory uses the upper
address byte. A typical memory access waveform is shown below.
As a special feature, the CY545 performs a verify read after writing to the memory. This function
is provided in support of EEPROM memories, that require a long time to perform a write
operation, and cannot perform another random write or read while the first one is in progress.
Many of these memories support Data/ polling, in which at least one bit of data is inverted while
the memory is busy writing the byte. When a read is performed, the data read does not match
the data written until the write operation is complete. This change in data values indicates when
the memory is ready for the next operation.
The CY545 performs the verify read repeatedly until the data matches the value written, or a
time out occurs. For RAMs, the match will occur immediately, so the CY545 simply continues at
that point. For an EEPROM, the match will occur after the EEPROM write is finished, and the
CY545 waits during this time before going on to the next function. This feature is shown in the
waveforms below.
© 2002 Cybernetic Micro Systems
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Chapter 16 - Timing and Control
ETC [ ETC ]
