Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
CMOS 5.0 V
Function
Low-noise Output Buffer
Block type
FE09
Path
→
t 1
T
Block type
IN
OUT
MIN.
0.916
1.084
0.955
1.008
1.020
1.039
1.057
1.073
1.167
1.235
1.279
1.441
TYP. MAX. MIN.
TYP. MAX. MIN.
TYP. MAX.
Drivability
1mA
no resistor
with 50 KΩ P/D
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
1.645
1.882
1.725
1.692
1.884
1.708
1.968
1.756
2.224
1.997
2.473
2.307
4.180
3.717
4.512
2.976
5.201
2.899
5.557
2.928
6.635
3.380
7.702
3.908
0.044
0.078
0.031
0.042
0.022
0.030
0.020
0.025
0.018
0.020
0.017
0.017
0.059
0.105
0.042
0.056
0.031
0.041
0.029
0.034
0.026
0.027
0.026
0.022
0.086
0.152
0.065
0.080
0.053
0.056
0.050
0.044
0.049
0.032
0.049
0.027
A
A
A
A
A
A
→
→
→
→
→
→
Y
Y
Y
Y
Y
Y
FE04
FE01
FE02
FE03
FE06
2mA
3mA
FE09
1
5
6mA
FE04
FE01
1
1
5
5
9mA
12mA
18mA
24mA
FE02
FE03
FE06
1
1
1
5
5
5
Input
Output
Logic Diagram
Block type
FE09
Symbol Fan-in Symbol Fan-out
A
A
A
A
A
A
9.6
9.6
9.5
9.5
9.6
9.6
Y
Y
Y
Y
Y
Y
-
-
-
-
-
-
FE04
FE01
FE02
FE03
FE06
A
H01
N01
Y
Truth Table
A
Y
1
0
1
0
Block Library A13872EJ5V0BL
1 - 14
Block Library A13872EJ5V0BL
1 - 15
ETC [ ETC ]
