Chapter 2 Function Block
D-F/F with 2 to 1 Selector
Chapter 2 Function Block
Switching speed
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Low Gate type
Block type
IN
OUT
MIN.
TYP. MAX.
MIN.
0.011
0.010
0.011
0.010
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
Q output
QB output
Normal
Q output
QB output
(HH) 0.363
(HL) 0.410
(HH) 0.502
(HL) 0.489
0.555
0.663
0.828
0.771
1.000
1.226
1.572
1.409
1.500
1.500
1.660
0.000
0.000
0.000
1.951
1.001
1.227
1.500
1.500
1.650
0.000
0.000
0.000
1.607
1.005
0.960
1.470
1.470
1.630
0.010
0.010
0.000
1.385
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
D0
D1
C
1.0
1.0
1.0
1.0
Q
35
35
F641S
C
C
→
Q
Drivability
Name cells
Name cells
Name cells
Name cells
Name cells
Name cells
QB
→
QB
Low Power
A
F641S
10
F641SQ
9
F641SB
9
x1
x2
x4
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
D0
D1
A
D0
D1
A
0.680
0.680
0.680
0.270
0.270
0.250
0.684
Logic Diagram for "Normal"
Truth Table for "Normal"
C
D0
D1
C
A
Q
QB
D0 H01
D1 H02
N01
Q
(HH) 0.363
(HL) 0.409
0.556
0.663
0.011
0.010
0.015
0.013
0.021
0.017
D0
D1
C
1.0
1.0
1.0
1.0
Q
35
F641SQ
C
→
Q
0
1
X
X
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
D0
D1
A
D0
D1
A
0.680
0.680
0.680
0.270
0.270
0.250
0.583
A
C
A
H03
H04
X
X
X
X
N02 QB
1
X
X
Hold
Hold
C
(HH) 0.339
(HL) 0.346
0.542
0.545
0.011
0.011
0.015
0.014
0.022
0.020
D0
D1
C
1.0
1.0
1.0
1.0
QB
34
F641SB
C
→
QB
X:Irrelevant
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
D0
D1
A
D0
D1
A
0.680
0.680
0.680
0.270
0.280
0.260
0.544
A
Logic Diagram for "Q output"
Truth Table for "Q output"
D0
D1
C
A
Q
D0 H01
D1 H02
N01
Q
C
0
1
X
X
0
0
0
1
1
0
1
0
1
0
1
C
A
H03
H04
X
X
X
X
1
X
X
Hold
Hold
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
D0
D1
C
A
QB
D0 H01
D1 H02
0
1
X
X
0
0
0
1
1
0
1
1
0
C
A
H03
H04
X
X
X
X
1
N01 QB
1
0
X
X
Hold
Hold
X:Irrelevant
Block Library A13872EJ5V0BL
2 - 286
Block Library A13872EJ5V0BL
2 - 287
ETC [ ETC ]
