TCSRW—Timer control/status register W
H'B2
Watchdog timer
Bit
7
B6WI
1
6
TCWE
0
5
4
3
2
WDON
0
1
B0WI
1
0
WRST
0
B4WI TCSRWE B2WI
Initial value
Read/Write
1
0
1
*
*
*
*
R/(W)
R
R/(W)
R
R/(W)
R
R/(W)
R
Watchdog timer reset
0
[Clearing conditions]
• Reset by RES pin
• When TCSRWE = 1, and 0 is written in both B0WI and WRST
[Setting condition]
1
When TCW overflows and a reset signal is generated
Bit 0 write inhibit
0
1
Bit 0 is write-enabled
Bit 0 is write-protected
Watchdog timer on
0
1
Watchdog timer operation is disabled
Watchdog timer operation is enabled
Bit 2 write inhibit
0
1
Bit 2 is write-enabled
Bit 2 is write-protected
Timer control/status register W write enable
0
1
Data cannot be written to bits 2 and 0
Data can be written to bits 2 and 0
Bit 4 write inhibit
0
1
Bit 4 is write-enabled
Bit 4 is write-protected
Timer counter W write enable
0
1
Data cannot be written to TCW
Data can be written to TCW
Bit 6 write inhibit
0
1
Bit 6 is write-enabled
Bit 6 is write-protected
Note: * Write is permitted only under certain conditions.
438
ETC [ ETC ]
