RDR32—Receive data register 32
H'AD
SCI32
Bit
7
6
5
4
3
2
1
0
RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
TMA—Timer mode register A
H'B0
Timer A
Bit
7
TMA7
0
6
TMA6
0
5
4
3
2
TMA2
0
1
0
TMA5
0
—
1
TMA3
0
TMA1
0
TMA0
Initial value
Read/Write
0
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
Clock output select Internal clock select
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ø/32
ø/16
ø/8
Prescaler and Divider Ratio
TMA3 TMA2 TMA1 TMA0 or Overflow Period
Function
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSW
PSW
PSW
PSW
ø/8192
ø/4096
ø/2048
ø/512
ø/256
ø/128
ø/32
Interval
timer
ø/4
øW/32
øW/16
øW/8
øW/4
ø/8
1 s
Time
base
(when
using
32.768 kHz)
0.5 s
0.25 s
0.03125 s
PSW and TCA are reset
436
ETC [ ETC ]
