TCSRF—Timer control/status register F
H'B7
Timer F
Bit
7
OVFH
0
6
5
4
3
2
CMFL
0
1
0
CMFH OVIEH CCLRH OVFL
OVIEL CCLRL
Initial value
Read/Write
0
0
0
0
0
0
*
*
*
*
R/(W)
R/(W)
R/(W)
R/W
R/W
R/(W)
R/W
R/W
Counter clear L
0
1
TCFL clearing by compare match is disabled
TCFL clearing by compare match is enabled
Timer overflow interrupt enable L
0
1
TCFL overflow interrupt request is disabled
TCFL overflow interrupt request is enabled
Compare match flag L
0
Clearing conditions:
After reading CMFL = 1, cleared by writing 0 to CMFL
Setting conditions:
1
Set when the TCFL value matches the OCRFL value
Timer overflow flag L
0
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
Setting conditions:
1
Set when TCFL overflows from H'FF to H'00
Counter clear H
0
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
1
Timer overflow interrupt enable H
TCFH overflow interrupt request is disabled
TCFH overflow interrupt request is enabled
0
1
Compare match flag H
0
Clearing conditions:
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting conditions:
Set when the TCFH value matches the OCRFH value
Timer overflow flag H
0
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when TCFH overflows from H'FF to H'00
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
442
ETC [ ETC ]
