Appendix A CPU Instruction Set
A.1
Instructions
Operation Notation
Rd8/16
General register (destination) (8 or 16 bits)
General register (source) (8 or 16 bits)
General register (8 or 16 bits)
Condition code register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
Rs8/16
Rn8/16
CCR
N
Z
V
C
PC
SP
Stack pointer
#xx: 3/8/16
Immediate data (3, 8, or 16 bits)
Displacement (8 or 16 bits)
Absolute address (8 or 16 bits)
Addition
d: 8/16
@aa: 8/16
+
–
×
÷
Subtraction
Multiplication
Division
Logical AND
Logical OR
Exclusive logical OR
Move
→
—
Logical complement
Condition Code Notation
Symbol
↑
↓
*
Modified according to the instruction result
Not fixed (value not guaranteed)
Always cleared to 0
0
—
Not affected by the instruction execution result
398
ETC [ ETC ]
