Table 13-3 Output Levels
Data
M
0
0
1
1
0
1
0
1
Static
Common output
Segment output
Common output
Segment output
Common output
Segment output
Common output
Segment output
V1
V1
V2, V3
V1
V3
V2
V3
V2
VSS
VSS
V2, V3
VSS
V2
V1
VSS
V1
VSS
V1
VSS
V1
VSS
VSS
V1
VSS
V1
VSS
V1
VSS
V1
1/2 duty
1/3 duty
1/4 duty
V3
V2
V3
13.3.6
Operation in Power-Down Modes
In the H8/3887 Series, the LCD controller/driver can be operated even in the power-down modes.
The operating state of the LCD controller/driver in the power-down modes is summarized in table
13-4.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless øw, øw/2, or øw/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to
the LCD panel in this case, it is essential to ensure that øw, øw/2, or øw/4 is selected. In active
(medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be
modified to ensure that the frame frequency does not change.
Table 13-4 Power-Down Modes and Display Operation
Module
Mode
Reset Active
Runs Runs
Runs Runs
Sleep
Runs
Runs
Stops
Watch
Stops
Runs
Subactive Subsleep Standby Standby
Clock
ø
Stops
Runs
Stops
Stops
Runs
Stops
Stops
Stops*4
øw
Stops*1 Stops*4
Stops*2 Stops
Display ACT = “0” Stops Stops
operation
Stops
ACT = “1” Stops Functions Functions Functions Functions Functions Stops*2 Stops
3
3
3
*
*
*
Notes: 1. The subclock oscillator does not stop, but clock supply is halted.
2. The LCD drive power supply is turned off regardless of the setting of the PSW bit.
3. Display operation is performed only if øw, øw/2, or øw/4 is selected as the operating clock.
4. The clock supplied to the LCD stops.
368
ETC [ ETC ]
