9.6
Watchdog Timer
9.6.1
Overview
The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally.
1. Features
Features of the watchdog timer are given below.
•
•
Incremented by internal clock source (ø/8192 or øw/32).
A reset signal is generated when the counter overflows. The overflow period can be set from
from 1 to 256 times 8192/ø or 32/øw (from approximately 4 ms to 1000 ms when ø = 2.00
MHz).
•
Use of module standby mode enables this module to be placed in standby mode independently
when not used.
2. Block diagram
Figure 9-16 shows a block diagram of the watchdog timer.
TCSRW
TCW
øw/32
ø/8192
ø
PSS
Notation:
Reset signal
TCSRW: Timer control/status register W
TCW:
PSS:
Timer counter W
Prescaler S
Figure 9-16 Block Diagram of Watchdog Timer
233
ETC [ ETC ]
