APEX 20K Programmable Logic Device Family Data Sheet
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/ 800 workstations
–
–
–
Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
NativeLinkTM integration with popular synthesis, simulation,
and timing analysis tools
Quartus II SignalTapTM embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
–
Supports popular revision-control software packages including
PVCS, Revision Control System (RCS), and Source Code Control
System (SCCS )
Table 4. APEX 20K QFP, BGA & PGA Package Options & I/O Count
Notes (1), (2)
Device
144-Pin
TQFP
208-Pin
PQFP
240-Pin
PQFP
356-Pin BGA 652-Pin BGA 655-Pin PGA
RQFP
RQFP
EP20K30E
EP20K60E
EP20K100
92
92
125
148
159
151
143
144
136
151
189
183
175
174
168
152
196
252
246
271
277
101
92
EP20K100E
EP20K160E
EP20K200
88
EP20K200E
EP20K300E
EP20K400
271
376
408
502
488
488
488
488
502
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
4
Altera Corporation
ETC [ ETC ]
