APEX 20K Programmable Logic Device Family Data Sheet
Table 8. Comparison of APEX 20K & APEX 20KE Features
Feature
APEX 20K Devices
APEX 20KE Devices
MultiCore system integration
SignalTap logic analysis
32/64-Bit, 33-MHz PCI
Full support
Full support
Full support
Full support
Full compliance in -1, -2 speed
grades
Full compliance in -1, -2 speed grades
32/64-Bit, 66-MHz PCI
MultiVolt I/O
-
Full compliance in -1 speed grade
2.5-V or 3.3-V V
1.8-V, 2.5-V, or 3.3-V V
CCIO
CCIO
V
selected for device
V
selected block-by-block
CCIO
CCIO
Certain devices are 5.0-V tolerant
5.0-V tolerant with use of external resistor
ClockLock support
Clock delay reduction
Clock delay reduction
2× and 4× clock multiplication
m/(n × v) or m/(n × k) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift
LVDS support
Up to four PLLs
ClockShift, clock phase adjustment
Dedicated clock and input pins Six
Eight
I/O standard support
2.5-V, 3.3-V, 5.0-V I/O
1.8-V, 2.5-V, 3.3-V, 5.0-V I/O
2.5-V I/O
3.3-V PCI
Low-voltage complementary
metal-oxide semiconductor
(LVCMOS)
3.3-V PCI and PCI-X
3.3-V Advanced Graphics Port (AGP)
Center tap terminated (CTT)
Low-voltage transistor-to-transistor GTL+
logic (LVTTL)
LVCMOS
LVTTL
True-LVDS and LVPECL data pins
(in EP20K300E and larger devices)
LVDS and LVPECL clock pins (in all
devices)
LVDS and LVPECL data pins up to
156 Mbps (in -1 speed grade devices)
HSTL Class I
PCI-X
SSTL-2 Class I and II
SSTL-3 Class I and II
Memory support
Dual-port RAM
FIFO
CAM
Dual-port RAM
FIFO
RAM
ROM
RAM
ROM
Altera Corporation
7
ETC [ ETC ]
