APEX 20K Programmable Logic Device Family Data Sheet
Table 112. EP20K1500E External Bidirectional Timing Parameters
Symbol -1 Speed Grade -2 Speed Grade
Note (1)
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
2.70
0.00
2.00
3.06
0.00
2.00
3.21
0.00
2.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INSUBIDIR
INHBIDIR
5.99
7.90
7.90
6.67
8.68
8.68
7.22
8.98
8.98
OUTCOBIDIR
XZBIDIR
ZXBIDIR
4.61
0.00
0.50
5.12
0.00
0.50
INSUBIDIRPLL
INHBIDIRPLL
OUTCOBIDIRPLL
XZBIDIRPLL
ZXBIDIRPLL
2.46
4.36
4.36
2.80
4.81
4.81
Note to Tables 107 - 112:
(1) The timing information for these tables is preliminary.
Tables 113 and 114 show selectable I/ O standard input and output delays
for APEX 20KE devices. If you select an I/ O standard input or output
delay other than LVCMOS, add or subtract the selected speed grade to or
from the LVCMOS value.
Table 113. Selectable I/O Standard Input Delays
Symbol -1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Min
Max
Min
Max
Min
Max
LVCMOS
0.00
0.00
0.00
0.00
0.00
0.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL
2.5 V
0.00
0.04
0.05
1.8 V
–0.11
0.01
0.03
0.04
PCI
0.09
0.10
GTL+
–0.24
–0.32
–0.08
–0.17
–0.16
–0.12
0.00
–0.23
–0.21
0.03
–0.19
–0.47
–0.23
–0.32
–0.31
–0.12
0.00
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
LVDS
–0.06
–0.05
–0.12
0.00
CTT
AGP
0.00
0.00
0.00
Altera Corporation
111
ETC [ ETC ]
