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RTL8100CL 参数 Datasheet PDF下载

RTL8100CL图片预览
型号: RTL8100CL
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
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RTL8100C & RTL8100CL  
Datasheet  
5.2. PCI Interface  
Table 2. PCI Interface  
Symbol  
Type  
Pin No  
Description  
AD31-0  
T/S  
33, 34, 36, 37, 39, 40, PCI Address and Data Multiplexed Pins.  
42, 43, 47, 49, 50, 53,  
55, 57, 58, 59, 79, 82,  
83, 85, 86, 87, 89, 90,  
93, 95, 96, 97, 98, 103,  
104  
C/BE3-0  
CLK  
T/S  
I
44, 60, 77, 92  
28  
PCI Bus Command and Byte Enables Multiplexed Pins.  
Clock.  
This PCI Bus clock provides timing for all transactions and bus  
phases, and is input to PCI devices. The rising edge defines the start  
of each phase. The clock frequency ranges from 0 to 40MHz. For  
normal network operation, the RTL8100C(L) requires a minimum  
PCI clock frequency of 16.75MHz.  
DEVSELB  
FRAMEB  
S/T/S  
S/T/S  
68  
61  
Device Select.  
As a bus master, the RTL8100C (L) samples this signal to ensure that  
a PCI target recognizes the destination address for the data transfer.  
As a target, the RTL8100C(L) asserts this signal low when it  
recognizes its target address after FRAMEB is asserted.  
Cycle Frame.  
As a bus master, this pin indicates the beginning and duration of an  
access. FRAMEB is asserted low to indicate the start of a bus  
transaction. While FRAMEB is asserted, data transfer continues.  
When FRAMEB is deasserted, the transaction is in the final data  
phase.  
As a target, the device monitors this signal before decoding the  
address to check if the current transaction is addressed to it.  
Grant.  
GNTB  
I
29  
This signal is asserted low to indicate to the RTL8100C(L) that the  
central arbiter has granted ownership of the bus to the RTL8100C(L).  
This input is used when the RTL8100C(L) is acting as a bus master.  
Request.  
The RTL8100C(L) will assert this signal low to request the  
ownership of the bus from the central arbiter.  
Initialization Device Select.  
This pin allows the RTL8100C(L) to identify when configuration  
read/write transactions are intended for it.  
INTAB.  
REQB  
IDSEL  
INTAB  
T/S  
I
30  
46  
25  
O/D  
Used to request an interrupt. It is asserted low when an interrupt  
condition occurs, as defined by the Interrupt Status, Interrupt Mask  
and Interrupt Enable registers.  
Single-Chip Fast Ethernet Controller  
6
Track ID: JATR-1076-21 Rev. 1.06