RTL8100C & RTL8100CL
Datasheet
Bit
3
2
1
0
R/W
R
R
R
R
Symbol
OWN3
OWN2
OWN1
OWN0
Description
OWN bit of Descriptor 3.
OWN bit of Descriptor 2.
OWN bit of Descriptor 1.
OWN bit of Descriptor 0.
5.26. Basic Mode Control Register (Offset 0062h-0063h, R/W)
Table 26. Basic Mode Control Register
Bit
Name
Description/Usage
Default/Attribute
15
Reset
This bit sets the status and control registers of the PHY (register
0062-0074H) to the default state. This bit is self-clearing.
1: Software reset
0, RW
0: Normal operation
14
13
-
Reserved.
This bit sets the network speed.
1: 100Mbps
-
Spd_Set
0, RW
0: 10Mbps. This bit’s initial value comes from the 93C46
12
Auto Negotiation This bit enables/disables the NWay auto-negotiation function.
0, RW
Enable
(ANE)
1: Enable auto-negotiation, bit13 will be ignored.
0: Disables auto-negotiation, bit13 and bit8 will determine the
link speed and the data transfer mode, respectively. This bit’s
initial value comes from the 93C46.
Reserved.
11-10
9
-
-
Restart Auto
Negotiation
This bit allows the NWay auto-negotiation function to be reset.
1: Re-start auto-negotiation
0, RW
0: Normal operation
8
Duplex Mode
This bit sets the duplex mode.
0, RW
1: Full-duplex
0: Normal operation. This bit’s initial value comes from the
93C46.
7-0
-
Reserved.
-
5.27. Basic Mode Status Register (Offset 0064h-0065h, R)
Table 27. Basic Mode Status Register
Bit
Name
Description/Usage
Default/Attribute
15
100Base-T4
1: Enable 100Base-T4 support
0: Disable 100Base-T4 support
0, RO
14
13
12
11
100Base_TX_ FD 1: Enable 100Base-TX full-duplex support
0: Disable 100Base-TX full-duplex support
100BASE_TX_HD 1: Enable 100Base-TX half-duplex support
0: Disable 100Base-TX half-duplex support
1, RO
1, RO
1, RO
1, RO
10Base_T_FD
1: Enable 10Base-T full-duplex support
0: Disable 10Base-T full-duplex support
10_Base_T_HD 1: Enable 10Base-T half-duplex support
0: Disable 10Base-T half-duplex support
Single-Chip Fast Ethernet Controller
29
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
