RTL8100C & RTL8100CL
Datasheet
5.23. Multiple Interrupt Select Register
(Offset 005Ch-005Dh, R/W)
Note: The following is true when MulERINT=0 (bit17, RCR). When MulERINT=1, any received packet
invokes an early interrupt according to the MISR[11:0] setting in Early Mode.
If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to the RTL8100C(L),
RCR<ERTH[3:0]> will not be used to transfer data in early mode. This register will be written to the
received data length in order to make an early Rx interrupt for the unfamiliar protocol.
Table 23. Multiple Interrupt Select Register
Bit
15-12
11-0
R/W
-
R/W
Symbol
-
MISR11-0
Description
Reserved.
Multiple Interrupt Select Register.
Indicates that the RTL8100C(L) made an Rx interrupt after
transferring byte data into the system memory. If the value of these
bits is zero, there will be no early interrupt when the RTL8100C(L)
prepares to execute the first PCI transaction of the received data.
Bit1, 0 must be zero.
The ERTH3-0 bits should not be set to 0 when the multiple interrupt
select register is used.
5.24. PCI Revision ID (Offset 005Eh, R)
Table 24. PCI Revision ID
Bit
R/W
Symbol
Description
7-0
R
Revision ID
The value in PCI Configuration Space offset 08h is 10h.
5.25. Transmit Status of All Descriptors (TSAD) Register
(Offset 0060h-0061h, R/W)
Table 25. Transmit Status of All Descriptors (TSAD) Register
Bit
15
14
13
12
11
10
9
8
7
6
5
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Symbol
TOK3
TOK2
TOK1
TOK0
TUN3
TUN2
TUN1
TUN0
TABT3
TABT2
TABT1
TABT0
Description
TOK bit of Descriptor 3.
TOK bit of Descriptor 2.
TOK bit of Descriptor 1.
TOK bit of Descriptor 0.
TUN bit of Descriptor 3.
TUN bit of Descriptor 2.
TUN bit of Descriptor 1.
TUN bit of Descriptor 0.
TABT bit of Descriptor 3.
TABT bit of Descriptor 2.
TABT bit of Descriptor 1.
TABT bit of Descriptor 0.
4
Single-Chip Fast Ethernet Controller
28
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
