NT6881
11. Watch-Dog Timer (WDT)
The NT6881 has a watch-dog timer reset function that protects programs against system standstill. The clock of the WDT
is derived from the crystal oscillator. The WDT interval is about 0.15 seconds when operation frequency is 6MHz. The
timer must be cleared every 0.15 second during normal operation; otherwise, it will overflow and cause system reset.
(This cannot be disabled by software) Before watch-dog reset occurred, the software must clear watch-dog register by
writing #55H to CLRWDT ($000EH) register.
For example:
LDA #$55H
STA $000E
12. Power Control
The power off flag (POF) in the MODE_FG register indicates whether a reset is a warm start or a cold start reset. POF is
set by hardware when an external power VCC arises to its normal operating level, and must be cleared by software in the
cold reset initialization procedure. A warm start reset (POF = 0) occurs at a watch-dog reset or resume reset.
Address Register
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
$000FH MODE_FG
02H
-
-
-
-
-
-
POF
SUSF
R/W
13. Universal Serial Bus Interface
Please refer to UNIVERSAL SERIAL BUS specification Version 1.0 Chapter 7, 8, and 9.
14. Suspend and Resume
Suspend:
When SIE receives suspend signal, NT6881 generates SUSP interrupt request. In the SUSP interrupt service routine, the
software must carry out following steps:
1) Clear SUSP IRQ flag,
2) Store all the port status,
3) Force return lines (PORT2) pull-high,
4) Force scan lines (PORT0, PORT1 and P30, P31 or P32) pull-low,
5) Turn off LED output,
6) Clear watch-dog register.
After the above action has been completed, the software must then set SUSLO ($1EH) to #55H and SUSHI ($1FH) to
#AAH in order to enter the SUSPEND mode. Finally, oscillator stops in order to save power.
Resume:
When NT6881 receives a RESUME signal, the chip will resume and the firmware initializes itself. The initialization
process includes, checking the status of the POF bit in the MODE_FG register, whereas if the POF bit equals “1”, the
firmware will enter into a cold reset procedure and clears the POF bit. If the POF bit equals “ 0” , the firmware will enter into
a warm reset procedure. If indeed a warm reset begins, the firmware checks the SUSF bit in MODE_FG. Regarding the
SUSF bit, if it equals “ 1” , the firmware enters into the RESUME procedure and then clears the SUSF bit, however if SUSF
equals “ 0” , then the firmware enters into a Watchdog Reset procedure.
When any keyboard key is struck and the Remote_Wake_Up bit equals “ 1” , a RESUME signal will be sent to the host, and
the above procedure will repeat themselves.
12
ETC [ ETC ]
