SCLK
Modulator Symbol Clock Output
Output
SCLK is a clock output synchronous to internally
processed symbols and bytes; it is identical to OCLK/4.
The L64777 uses SCLK to determine the phase of the
Nyquist filter output. The rising edge of SCLK is followed
by Phase 0. The falling edge is the transition of Phase 1
to Phase 2 in 4-fold oversampling mode.
SSTARTIN
Sync Sequence Start
Input
The SSTARTIN pin is asserted to mark the beginning of
a new, fully reset sequence by a hardwired signal. The
L64777 evaluates the SSTARTIN negative slope and
restarts all internal sequences at the next Block/Frame
start following the negative SSTARTIN slope. If no
SSTARTIN is applied, all internal sequences run free
after the reset.
5.3 Status Information Signals
DIG_I[9:0]
Digital I Component
Output
This port provides modulator I-component output in
digital format. Depending on the PLL mode, either OCLK
or PCLK is the related clock.
DIG_Q[9:0]
Digital Q Component
Output
This port provides modulator Q-component output in
digital format. Depending on the PLL mode, either OCLK
or PCLK is the related clock.
FIFOALARM FIFO Collision Detected
Output
If this alarm occurs, the FIFO control has detected equal
pointers for read and write access. A detected collision
most probably indicates unlocked external PLL-VCO
circuitry. The L64777 synchronizes this signal with
SCLK-driven flip-flops for the output.
FIRSTOUT
First Block of New Sequence Out
Output
FIRSTOUT occurs together with FSTARTOUT and
indicates the head of a sync block that has just-reset
sequences, as controlled by SSTARTIN. FIRSTOUT is
the acceptance of a SSTARTIN negative slope delayed
by all internal processing modules.
5-4
Signals
ETC [ ETC ]
