5.2 MPEG Transport Stream Multiplexer Signals
DIN[7:0]
QAM Modulator Parallel/Serial Data In
Input
Serial data enters the L64777 on DIN[0]; parallel data
enters on DIN[7:0]. The modulator samples DIN[7:0] at
the positive edge of ICLK. The DIN[7:0] input accepts
data with any number of invalid bits in between. The
modulator disregards invalid bits or bytes and does not
take them into the input FIFO.
DVALIDIN
Clock Enable Input
Input
When DVALIDIN is active (HIGH), the L64777 accepts
data from DIN[7:0] on a continuous basis. When
DVALIDIN is LOW, data input to the internal FIFO and
internal data processing stops, and the encoder does not
accept new input from the DIN[7:0] pins. DVALIDIN
functions independently of the modulator.
ERRORIN
FSTARTIN
Error Detection Flag
Input
The ERRORIN pin is asserted to flag uncorrectable
errors. The L64777 checks the ERRORIN status at the
first bit of a frame; then, if required (HIGH = set error bit),
it copies the value of that bit to the MPEG error-indication
bit.
External Sync Input
Input
The FSTARTIN pin is asserted to mark the beginning of
an MPEG transport packet by a hardwired signal. If the
incoming bitstream contains no unique sync words, this
pulse must be applied to the L64777. The L64777 forces
synchronization with FSTARTIN pulses into the chip; it
does not flywheel-stabilize synchronization as in the sync
word detection mode. In the sync insertion mode, the
L64777 regenerates the DVB-defined sync information
and inserts it into the QAM Modulator.
ICLK
QAM Modulator Input Clock
Input
ICLK is a positive-edge-triggered clock. The L64777
clocks DIN[7:0], DVALIDIN, ERRORIN, FSTARTIN and
SSTARTIN on the rising edge of ICLK. ICLK is either a
byte clock or a bit clock, depending on the control register
(Register 1) setup for parallel/serial mode.
MPEG Transport Stream Multiplexer Signals
5-3
ETC [ ETC ]
