HT46R47
clock setting register (ACSR;23H), I/O regis-
ters (PA;12H, PB;14H, PD;18H) and I/O con-
trol registers (PAC;13H, PBC;15H, PDC;19H).
The remaining space before the 40H is re-
served for future expanded usage and reading
these locations will get "00H". The general
purpose data memory, addressed from 40H to
7FH, is used for data and control information
under instruction commands.
All of the data memory areas can handle arith-
metic, logic, increment, decrement and rotate
operations directly. Except for some dedicated
bits, each bit in the data memory can be set and
reset by "SET [m].i" and "CLR [m].i". They are
also indirectly accessible through memory
pointer register (MP;01H).
Indirect addressing register
Location 00H is an indirect addressing register
I
n
d
i
r
e
c
t
A
d
d
r
e
s
s
i
n
g
R
e
g
i
s
t
e
r
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
that is not physically implemented. Any
read/write operation of [00H] accesses data mem-
ory pointed to by MP (01H). Reading location 00H
itself indirectly will return the result 00H. Writ-
ing indirectly results in no operation.
M
P
A
C
C
P
C
L
The memory pointer register MP (01H) is a 7-bit
register. The bit 7 of MP is undefined and reading
will return the result ²1². Any writing operation to
MP will only transfer the lower 7-bit data to MP.
T
B
L
P
T
B
L
H
S
T
A
T
U
S
0
0
A
B
H
H
S
p
e
c
i
a
l
P
u
r
p
o
s
e
I
N
T
C
D
A
T
A
M
E
M
O
R Y
Accumulator
0
0
C
D
H
H
T
M
R
The accumulator is closely related to ALU oper-
ations. It is also mapped to location 05H of the
data memory and can carry out immediate data
operations. The data movement between two
data memory locations must pass through the
accumulator.
T
M
R
C
0
E
H
0
F
H
H
H
H
H
H
H
H
H
H
H
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
P
P
A
B
P
P
A
B
C
C
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic
operations. The ALU provides the following func-
tions:
P
D
:
U
n
u
s
e
d
P
D
C
1
1
A
B
H
H
P
W
M
R
e
a
d
a
s
"
0
0
"
·
Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
1
1
C
D
H
H
·
·
·
·
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
1
E
H
1
F
H
2
2
2
0
1
2
H
H
H
A
D
R
L
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
A
A
D
D
R
C
H
R
The ALU not only saves the results of a data op-
eration but also changes the status register.
2
3
H
A
C
S
R
2
3
4
F
H
H
4
0
H
Status register - STATUS
G
e
A
n
e
r
a
l
P
u
r
p
o
s
e
D
T
A
M
E
M
O
R
Y
This 8-bit register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD), and
watchdog time-out flag (TO). It also records the
(
6
4
B
y
t
e
s
)
7
F
H
RAM mapping
Rev. 1.40
9
July 18, 2001
ETC [ ETC ]
