HT46R47
version control bit and the end of A/D conver-
sion flag. If the users want to start an A/D
conversion, define PB configuration, select the
converted analog channel, and give START bit
a raising edge and a falling edge (0®1®0). At
the end of A/D conversion, the EOC bit is
cleared and an A/D converter interrupt occurs
(if the A/D converter interrupt is enabled). The
ACSR is A/D clock setting register, which is
used to select the A/D clock source.
PB line is selected as an analog input, the I/O
functions and pull-high resistor of this I/O line
are disabled, and the A/D converter circuit is
power on. The EOC bit (bit6 of the ADCR) is
end of A/D conversion flag. Check this bit to
know when A/D conversion is completed. The
START bit of the ADCR is used to begin the
conversion of A/D converter. Give START bit a
raising edge and falling edge that means the
A/D conversion has started. In order to ensure
the A/D conversion is completed, the START
should stay at ²0² until the EOC is cleared to
²0² (end of A/D conversion).
The A/D converter control register is used to
control the A/D converter. The bit2~bit0 of the
ADCR are used to select an analog input chan-
nel. There are a total of four channels to select.
The bit5~bit3 of the ADCR are used to set PB
configurations. PB can be an analog input or as
digital I/O line decided by these 3 bits. Once a
The bit 7 of the ACSR is used for testing pur-
pose only. It can not be used for the users. The
bit1 and bit0 of the ACSR are used to select A/D
clock sources.
Label (ADCR)
Bits
Function
ACS2, ACS1, ACS0: Select A/D channel
0, 0, 0: AN0
ACS0
ACS1
ACS2
0
1
2
0, 0, 1: AN1
0, 1, 0: AN2
0, 1, 1: AN3
1, X, X: undefined, cannot be used
PCR2, PCR1, PCR0: PB3~PB0 configurations
0, 0, 0: PB3 PB2 PB1 PB0 (The ADC circuit is power off to reduce
power consumption.)
PCR0
PCR1
PCR2
3
4
5
0, 0, 1: PB3 PB2 PB1 AN0
0, 1, 0: PB3 PB2 AN1 AN0
0, 1, 1: PB3 AN2 AN1 AN0
1, x, x: AN3 AN2 AN1 AN0
End of A/D conversion flag.
(0: end of A/D conversion)
EOC
6
7
Start the A/D conversion
0®1®0: Start
START
0®1: Reset A/D converter and set EOC to ²1²
Bits
Function
ADCS1, ADCS0: Select the A/D converter clock source.
0, 0: fSYS/2
ADCS0
ADCS1
0
1
0, 1: fSYS/8
1, 0: fSYS/32
1, 1: Undefined, cannot be used.
¾
2~6 Unused bit, read as ²0².
TEST
7
For internal test only.
20
Rev. 1.40
July 18, 2001
ETC [ ETC ]
