HT46R47
on pull-high options). Each bit of these in-
put/output latches can be set or cleared by ²SET
[m].i² and ²CLR [m].i² (m=12H, 14H or 18H) in-
structions.
erated by timer/event counter overflow signal.
The input mode always remaining its original
functions. Once the PFD option is selected, the
PFD output signal is controlled by PA3 data
register only. Writing ²1² to PA3 data register
will enable the PFD output function and writ-
ing ²0² will force the PA3 to remain at ²0². The
I/O functions of PA3 are shown below.
Some instructions first input data and then fol-
low the output operations. For example, ²SET
[m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or the accu-
mulator.
I/O
Mode (Normal)(Normal) (PFD) (PFD)
Logical Logical Logical PFD
Input Output Input (Timer on)
I/P
O/P
I/P
O/P
PA3
Each line of port A has the capability of wak-
ing-up the device. The highest 4-bit of port B and
7 bits of port D are not physically implemented;
on reading them a ²0² is returned whereas writ-
ing then results in a no-operation. See Applica-
tion note.
Note: The PFD frequency is the timer/event
counteroverflowfrequencydividedby2.
The PA5 and PA4 are pin-shared with INT and
TMR pins respectively.
Each I/O line has a pull-high option. Once the
pull-high option is selected, the I/O line has a
pull-high resistor, otherwise, there¢s none.
Take note that a non-pull-high I/O line operat-
ing in input mode will cause a floating state.
The PB can also be used as A/D converter in-
puts. The A/D function will be described later.
There is a PWM function shared with PD0. If
the PWM function is enabled, the PWM signal
will appear on PD0 (if PD0 is operating in out-
put mode). The I/O functions of PD0 are as
shown.
The PA3 is pin-shared with the PFD signal. If
the PFD option is selected, the output signal in
output mode of PA3 will be the PFD signal gen-
V
D
D
C
o
n
t
r
o
l
B
i
t
P
U
D
s
Q
D
a
t
a
B
u
W
r
i
t
e
C
o
n
t
r
e
o
C
l
K
Q
R
B
e
g
i
s
t
e
r
S
t
P
P
P
P
P
P
P
A
A
A
A
0
3
4
5
~
/
/
/
P
A
2
C
h
i
p
R
s
e
P
T
I
F
D
M
R
N
P
T
R
e
a
d
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
A
6
0
,
/
A
7
D
a
t
a
B
i
t
B
D
A
N
0
~
P
B
3
/
A
N
3
D
C
Q
0
/
P
W
M
K
Q
B
g
W
r
i
t
e
D
a
t
a
R
e
i
s
t
e
r
S
M
U
P
A
3
(
P
D
0
o
r
P
W
M
)
X
P
F
D
P
F
D
E
N
M
(
P
A
3
)
U
X
R
e
a
d
D
a
t
a
R
e
g
i
s
t
e
r
S
y
s
t
e
m
W
a
k
e
-
u
p
O
P
0
~
O
P
7
(
P
A
o
n
l
y
)
I
N
T
f
o
r
P
A
5
O
n
l
y
T
M
R
f
o
r
P
A
4
O
n
l
y
Input/output ports
18
Rev. 1.40
July 18, 2001
ETC [ ETC ]
