CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Switching Waveforms
[27, 28]
Read Timing
tKC
tKL
CLK
tKH
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
tH
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
tS
CE#
ADV#
OE#
DQ
tS
tH
tKQ
tKQ
tOEQ
tOELZ
tKQLZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
SINGLE READ
BURST READ
Notes:
27. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active.
28. For X18 product, there are only BWa and BWb for byte write control.
19