Register Description
3.3.37
MBFS—Memory Buffer Frequency Select Register
(Device 0)
Address Offset:
Default Value:
Access:
CA–CCh
000000h
Read/Write
24 bits
Size:
The settings in this register enable the 100 MHz or 66 MHz buffers for each of the following signal
groups.
Note: The choice of 100 MHz or 66 MHz buffer is independent of bus frequency. It is possible to select a
100 MHz memory buffer even though the bus frequency is 66 MHz (and vice versa).
Bit
Description
23
Reserved
MAA[13:0], WEA#, SRASA#, SCASA# (100 MHz/66 MHz buffer select bit). This bit enables
either 100 MHz or 66 MHz buffers for MAA[13:0], WEA#, SRASA#, SCASA#.
22
21
0 = 66 MHz
1 = 100 MHz
MAB[12:11, 9:0]# & MAB[13,10], WEB#, SRASB#, SCASB# (100 MHz/66 MHz buffer select
bit). This bit enables either 100 MHz or 66 MHz buffers for MAB[12:11, 9:0]# & MAB[13,10],
WEB#, SRASB#, SCASB#. Note that the address’s MABx# are inverted copies of MAA, with the
exception of MAB[13,10].
0 = 66 MHz
1 = 100 MHz
MD [63:0] (100 MHz/66 MHz buffer select bit [Control 2]). This bit enables either 100 MHz or
66 MHz buffers for MD [63:0] [Control 2]. (Refer to the corresponding MBSC register for
programming details).
20
19
18
0 = 66 MHz
1 = 100 MHz
MD [63:0] (100 MHz/66 MHz buffer select bit [Control 1]). This bit enables either 100 MHz or
66 MHz buffers for MD [63:0] [Control 1]. (Refer to the corresponding MBSC register for
programming details).
0 = 66 MHz
1 = 100 MHz
MECC [7:0] (100 MHz/66 MHz buffer select bit [Control 2]). This bit enables either 100 MHz or
66 MHz buffers for MECC [7:0] [Control 2]. (Refer to the corresponding MBSC register for
programming details).
0 = 66 MHz
1 = 100 MHz
MECC [7:0] (100 MHz/66 MHz buffer select bit [Control 1]). This bit enables either 100 MHz or
66 MHz buffers for MECC [7:0] [Control 1]. (Refer to the corresponding MBSC register for
programming details).
17
16
0 = 66 MHz
1 = 100 MHz
CSB7#/CKE5 (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz
buffers for CSB7#/CKE5.
0 = 66 MHz
1 = 100 MHz
3-42
82443BX Host Bridge Datasheet
ETC [ ETC ]
