TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
24. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022
response from the Software Status Register. This clears the STATUS READY bit.
25. Repeat steps 22-24 until all (16) data words are transferred
26. CT8022 de-asserts DATAFLAG/ signal to indicate the end of data transfer
27. Optional: Host waits for DATAFLAG/ to be de-asserted
28. Repeat steps 13-27 until playback finished
To end playback Host writes Idle command or Playback Stop command and waits for status response.
Note: Bold text indicates the playback software data transfer loop. By default, The DATAFLAG signal on
external pin GPIO0 is disabled. Refer to Section 9.25 for more information regarding GPIO pins.
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DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
