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CT8022A11AQC 参数 Datasheet PDF下载

CT8022A11AQC图片预览
型号: CT8022A11AQC
PDF下载: 下载PDF文件 查看货源
内容描述: VOIP / VON G.723.1 , G279AB TRUESPEECH协处理器 [VOIP/VON G.723.1, G279AB TRUESPEECH CO-PROCESSOR]
分类和应用:
文件页数/大小: 194 页 / 1455 K
品牌: ETC [ ETC ]
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TrueSpeech® Co-Processor  
PRELIMINARY/CONFIDENTIAL  
Version: 1.18  
Example 3: Linear 16-bit Playback via Host Transmit Data Buffer Access Port - Using DMA  
This example shows how to start playback in uncompressed 16-bit Linear Format Speech with data transfers  
performed via the Host Transmit Data Buffer Access Port. An external DMA controller performs all data transfers  
in this example.  
Starting Playback  
1. CT8022 is in IDLE state or RECORD state.  
2. Host checks for CONTROL READY state in Hardware Status Register.  
3. Host selects Poll Sync Mode for playback using the command 5202H.  
4. CT8022 responds via the Software Status Register.  
5. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response  
from the Software Status Register. This clears the STATUS READY bit.  
6. Host selects Playback by issuing the PLAYBACK C1 command = 2C63H or 2C61H (PLAYMODE = [binary]  
110) via the Software Control Register. This also informs the CT8022 that data transfers will occur via the Host  
Transmit Data Buffer Access Port (TFR Mode = [binary] 11 or 01).  
7. CT8022 responds via the Software Status Register after a delay of up to 2 speech frame periods.  
8. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response  
from the Software Status Register S1 = 2C63H or 2C61H. This clears the STATUS READY bit.  
9. Host writes PLAYBACK C2 command = 2000H to the Software Control Register.  
10. CT8022 responds via the Software Status Register.  
11. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response  
from the Software Status Register S2 = 2000H. This clears the STATUS READY bit.  
12. Host writes PLAYBACK C3 command = 20F0H to the Software Control Register. This command includes the  
requested number of words per frame to transfer. In this case (uncompressed 16-bit linear) this is 240 = F0H.  
13. CT8022 responds via the Software Status Register.  
14. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response  
from the Software Status Register S3 = 2000H. This clears the STATUS READY bit. The S3 response sets the  
actual number of words to transfer to 00H. This transfer count indicates the number of words to be transferred  
via the Software Control and Status Registers. Since this example uses TFR Mode = [binary] 11, no data is  
transferred via the Software Control and Status Registers, instead the data transfer takes place via the Host  
Transmit Data Buffer Access Port.  
15. Host programs external DMA controller to accept DMA requests from the CT8022 (See DMA Direction bit in  
Hardware Control Register). Host configures a data buffer in the Host memory to store the speech data ready  
for DMA. The DMA memory buffer should be an integral multiple of the speech frame size. In the case of  
uncompressed 16-bit Linear, this should be N*480 (bytes).  
16. Host sets up an ISR to handle an end-of-transfer (EOT) interrupt from the DMA controller when it reaches the  
end of the DMA buffer. Alternatively, if the DMA supports circular-buffering (auto-initialize), the Host can  
poll the DMA to determine when the end of the buffer is reached.  
17. Host programs the Hardware Control Register to generate a DMA request from the CT8022 on the TX Ready  
condition by writing 00A0H ( TX DMA Burst Mode, TX DMA enable) - or 01A0H (TX DMA Burst Mode,  
TX DMA enable, DMA Direction bit set).  
18. The CT8022 is now in playback mode. The CT8022 will consume an uncompressed speech frame every 30ms.  
The following sequence occurs between the CT8022 and the DMA controller to transfer data:  
a. CT8022 is ready to receive 240 words (480 bytes) of uncompressed 16-bit speech data.  
b. CT8022 asserts TX Ready.  
c. TX Ready drives TXDREQ.  
d. DMA controller responds to TXDREQ by asserting TXDACKN.  
e. DMA controller performs a burst transfer of 16 words (32 bytes) from the Host DMA memory buffer to the  
CT8022.  
f. CT8022 de-asserts TX Ready.  
g. CT8022 transfers 16 words from the Host Transmit Data Buffer into its internal playback buffer.  
h. Repeat b-g until all 240 words of the speech data frame have been transferred.  
76  
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118  
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490  
All specifications are subject to change without prior notice.  
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