VS1000
7
FIRMWARE OPERATION
7 Firmware Operation
The firmware uses the following pins (see the example schematics in Section 5):
Pin Description
PWRBTN High level starts regulator, is also read as the Power button Key.
GPIO0_0 external 100 kΩ pull-down resistor, Key 1 connects a 10 kΩ pull-up resistor
GPIO0_1 external 100 kΩ pull-down resistor, Key 2 connects a 10 kΩ pull-up resistor
GPIO0_2 external 100 kΩ pull-down resistor, Key 3 connects a 10 kΩ pull-up resistor
GPIO0_3 external 100 kΩ pull-down resistor, Key 4 connects a 10 kΩ pull-up resistor
GPIO0_4 external 100 kΩ pull-down resistor, Key 5 connects a 10 kΩ pull-up resistor
GPIO0_6 external pull-down resistor for USB Mass Storage Device, pull-up for USB Audio Device
GPIO0_7 external pull-down resistor for 1.8 V I/O voltage, pull-up resistor for 3.3 V I/O voltage
NFCE
NFRDY
XCS
SI
SO
external pull-up resistor for normal operation, pull-down to use RAM disk for UMS Device
external 10 kΩ pull-up resistor
external pull-up to enable SPI EEPROM boot, pull-down to disable
Power LED control during firmware operation
Feature LED control during firmware operation
external 1 MΩ pull-up resistor
USBN
USBP
external 1 MΩ pull-up resistor
Boot order:
Stage
Description
Power on
Reset
Power button (PWRBTN) pressed when VHIGH has enough voltage
Power-on reset, XRESET, or watchdog reset causes software restart
UART Boot
Almost immediately after power-on UART can be used to enter emulator mode.
SPI EEPROM Boot
If XCS is high, SPI Boot is tried.
NAND FLASH probed If NFCE is high, NAND FLASH is checked using 660 ns read/write low time.
Default firmware
The firmware in ROM takes control.
7.1 SPI Boot
The first boot method is SPI EEPROM. If GPIO1_0 is low after reset, SPI boot is skipped. If
GPIO1_0 is high, it is assumed to have a pull-up resistor and SPI boot is tried.
First the first four bytes of the SPI EEPROM are read using 16-bit address. If the bytes are
“VLSI”, a 16-bit EEPROM is assumed and the boot continues. If the last 3 bytes are read as
“VLS”, a 24-bit EEPROM is assumed and boot continues in 24-bit mode. Both 16-bit and 24-bit
EEPROM should have the “VLSI” string starting at address 0, and the rest of the boot data
starting at address 4. If no identifier is found, SPI EEPROM boot is skipped.
Boot records are read from EEPROM until an execute record is reached. Unknown records are
skipped using the data length field.
Byte Description
0
1,2
3, 4
type 0=I-mem 1=X-mem 2=Y-mem 3=execute
data len lo, hi – data length in bytes
address lo, hi – record address
5..
data*
Version: 1.4, 2011-10-06
16
ETC [ ETC ]
