VS1000
6.2
Digital Section
6
VS1000 FUNCTIONAL BLOCKS
Two of the regulators provide power supply for the digital section.
IOVDD is used for the level-shifters of the digital I/O and crystal oscillator. The IOVDD regulator
output must be connected to IOVDD1 and IOVDD2 input pins, because they are not connected
internally. Proper bypass capacitors should also be used.
The firmware uses GPIO0_7 to select I/O voltage level. After reset the I/O voltage is 1.8 V. If
GPIO0_7 has a pull-down resistor, 1.8 V I/O voltage is used. If GPIO0_7 has a pull-up resistor,
3.3 V I/O voltage is used.
All other digital is powered from core voltage (CVDD). The core voltage is internally connected,
and the CVDD pin should have a proper bypass capacitors.
Clock
The crystal amplifier uses a crystal connected to XTALI and XTALO. An external logic-level
input clock can also be used. When VS1000 is used with USB, 12 MHz input clock must be
used.
An internal phase-locked loop (PLL) generates the internal clock by multiplying the input clock
by 1.0×, 1.5×, . . . , 4.0×. When USB is connected, the clock is 4.0×12 MHz = 48 MHz. When
the player is active, the clock will be automatically changed according to the requirements of
the song being played.
XRESET disables the clock buffer and puts the digital section into powerdown mode.
VSDSP
4
VSDSP
4
is VLSI Solution’s proprietary digital signal processor with a 32-bit instruction word,
two 16-bit data buses, and both 16-bit and 32/40-bit arithmetic.
IROM, XROM, and YROM contain the firmware, including the default player application. Most
of the instruction RAM and some of the X and Y data RAM’s can be used to customize and
extend the functionality of the player.
UART
An asynchronous serial port is used for debugging and special applications. The default speed
is 115200 bps. RX and TX pins can also be used for general-purpose I/O when the UART is
not required.
Version: 1.4, 2011-10-06
13
ETC [ ETC ]
