CXD3018Q/R
§5-15. Writing to Coefficient RAM
The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and
transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin
rises. (The coefficient RAM cannot be rewritten during this period.)
After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address
of the coefficient RAM.
The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and
D7 to D0 as the data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is
received. When rewriting multiple coefficients continuously, be sure to wait 11.3µs (when MCK = 128Fs)
before sending the next rewrite command.
§5-16. PWM Output
FCS, TRK and SLD PWM format outputs are described below.
In particular, FCS and TRK use a double oversampling noise shaper.
Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits.
MCK
(5.6448MHz)
↑
↑
↑
↑
↑
↑ ↑
Output value +A
Output value –A
Output value 0
64tMCK
SLD
64tMCK
64tMCK
SFDR
SRDR
AtMCK
AtMCK
FCS/TRK
32tMCK
32tMCK
32tMCK
32tMCK
32tMCK
32tMCK
FFDR/
TFDR
A
2
A
2
tMCK
tMCK
FRDR/
TRDR
A
2
A
2
tMCK
tMCK
1
tMCK =
≈ 180ns
5.6448MHz
Timing Chart 5-20
VCC
R
R
DRV
RDR
FDR
R
R
VEE
Fig. 5-21. Drive Circuit
– 99 –
ETC [ ETC ]
