CXD3018Q/R
§5-13. COUT Signal
The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among
three different phases according to the COUT signal application.
• HPTZC: For 1-track jumps
Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by
a cut-off 1kHz digital HPF; when MCK = 128Fs.)
• STZC: For COUT generation when MIRR is externally input and for applications other than COUT generation.
This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
• DTZC: For high-speed traverse
Reliable COUT signal generation with a delayed phase STZC signal.
Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance
with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D15 and D14 of $3C.
When D15 = 1:
STZC
When D15 = 0 and D14 = 0: HPTZC
When D15 = 0 and D14 = 1: DTZC
When DTZC is selected, the delay can be selected from two values with D14 of $36.
§5-14. Serial Readout Circuit
The following measurement and adjustment results specified beforehand by serial command $39 can be read
out from the SENS pin by inputting the readout clock to the SCLK pin. (See Fig. 5-18, Table 5-19 and
"Description of SENS Signals".)
Specified commands
$390C: VC AVRG measurement result
$3908: FE AVRG measurement result
$3904: TE AVRG measurement result
$391F: RF AVRG measurement result
$3953: FCS AGCNTL coefficient result
$3963: TRK AGCNTL coefficient result
$391C: TRVSC adjustment result
$391D: FBIAS register value
XLAT
tSPW
tDLS
...
SCLK
1/fSCLK
Serial Readout Data
(SENS pin)
...
MSB
LSB
Fig. 5-18
Symbol
Max.
16
Unit
Item
SCLK frequency
SCLK pulse width
Delay time
Min.
Typ.
fSCLK
MHz
ns
t
SPW
DLS
31.3
15
t
µs
Table 5-19
During readout, the upper 8 bits of the command register must be 39 (h).
– 98 –
ETC [ ETC ]
