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CXD3018Q/R 参数 Datasheet PDF下载

CXD3018Q/R图片预览
型号: CXD3018Q/R
PDF下载: 下载PDF文件 查看货源
内容描述: CD数字信号处理器,内置DigitalServo和DAC [CD Digital Signal Processor with Built-in DigitalServo and DAC ]
分类和应用: 数字信号处理器
文件页数/大小: 134 页 / 942 K
品牌: ETC [ ETC ]
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CXD3018Q/R  
§5-17. Servo Status Changes Produced by LOCK Signal  
When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off  
in order to prevent SLD free-running.  
Setting D6 (LKSW) of $38 to 1 deactivates this function.  
In other words, neither the TRK servo nor the SLD servo changes even when the LOCK signal becomes low.  
This enables microcomputer control.  
§5-18. Description of Commands and Data Sets  
$34  
D15 D14 D13 D12 D11 D10 D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
KA6 KA5 KA4 KA3 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0  
When D15 = 0.  
KA6 to KA0: Coefficient address  
KD7 to KD0: Coefficient data  
$348 (preset: $348 000)  
D15 D14 D13 D12 D11 D10 D9  
D8  
D7  
0
D6  
0
D5  
0
D4  
D3  
D2  
D1  
0
D0  
0
1
0
0
0
0
0
PFOK1 PFOK0  
MRS MRT1 MRT0  
These commands set the FOK signal hold time. See $3B for the FOK slice level.  
These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting.  
PFOK1 PFOK0  
Processing  
High when the RFDC value is higher than the FOK slice level, low when lower than the  
FOK slice level.  
0
0
1
1
0
1
0
1
High when the RFDC value is higher than the FOK slice level, low when continuously  
lower than the FOK slice level for 4.35ms or more.  
High when the RFDC value is higher than the FOK slice level, low when continuously  
lower than the FOK slice level for 10.16ms or more.  
High when the RFDC value is higher than the FOK slice level, low when continuously  
lower than the FOK slice level for 21.77ms or more.  
MRS:  
This command switches the time constant for generating the MIRR comparator level of the MIRR  
generation circuit.  
When 0, the time constant is normal. (default)  
When 1, the time constant is longer than normal.  
The time during which MIRR = high due to the effects of RFDC signal pulse noise, etc., can be  
suppressed by setting MRS = 1.  
MRT1, 0:  
These commands limit the time while MIRR = high.  
MRT1  
MRT0  
MIRR maximum time [ms]  
0
0
1
1
No time limit  
1.10  
0
1
0
1
2.20  
4.00  
: preset  
100 –  
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