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CXD3018Q/R 参数 Datasheet PDF下载

CXD3018Q/R图片预览
型号: CXD3018Q/R
PDF下载: 下载PDF文件 查看货源
内容描述: CD数字信号处理器,内置DigitalServo和DAC [CD Digital Signal Processor with Built-in DigitalServo and DAC ]
分类和应用: 数字信号处理器
文件页数/大小: 134 页 / 942 K
品牌: ETC [ ETC ]
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CXD3018Q/R  
§5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.)  
The CXD3018Q/R can measure the averages of RFDC, VC, FE and TE and compensate these signals using  
the measurement results to control the servo effectively. This AVRG measurement and compensation is  
necessary to initialize the CXD3018Q/R, and is able to cancel the DC offset.  
AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average values  
of 256 samples, and then loads these values into each AVRG register.  
The AVRG measurement commands are D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TLM) of $38.  
Measurement is on when the respective command is set to 1.  
AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received.  
The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.)  
Monitoring requires that the upper 8 bits of the command register are 38 (h).  
XLAT  
2.9 to 5.8ms  
SENS  
(= XAVEBSY)  
AVRG measurement completed  
Max. 1µs  
Timing Chart 5-2  
<Measurement>  
VC AVRG: The VC DC offset (VC AVRG) which is the center voltage for the system is measured and used to  
compensate the FE, TE and SE signals.  
FE AVRG: The FE DC offset (FE AVRG) is measured and used to compensate the FE and FZC signals.  
TE AVRG: The TE DC offset (TE AVRG) is measured and used to compensate the TE and SE signals.  
RF AVRG: The RF DC offset (RF AVRG) is measured and used to compensate the RFDC signal.  
<Compensation>  
RFLC:  
(RF signal RF AVRG) is input to the RF In register.  
"00" is input when the RF signal is lower than RF AVRG.  
(TE signal VC AVRG) is input to the TRK In register.  
(TE signal TE AVRG) is input to the TRK In register.  
(FE signal VC AVRG) is input to the FCS In register.  
(FE signal FE AVRG) is input to the FCS In register.  
(FE signal FE AVRG) is input to the FZC register.  
TCL0:  
TCL1:  
VCLC:  
FLC1:  
FLC0:  
Two methods of canceling the DC offset are assumed for the CXD3018Q/R. These methods are shown in  
Figs. 5-3a and 5-3b.  
An example of AVRG measurement and compensation commands is shown below.  
$38 08 00 (RF AVRG measurement)  
$38 20 00 (FE AVRG measurement)  
$38 00 10 (TE AVRG measurement)  
$38 14 0A (Compensation on [RFLC, FLC0, FLC1, TLC1]; corresponds to Fig. 5-3a.)  
See the description of $38 for these commands.  
88 –  
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