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CXD3018Q/R 参数 Datasheet PDF下载

CXD3018Q/R图片预览
型号: CXD3018Q/R
PDF下载: 下载PDF文件 查看货源
内容描述: CD数字信号处理器,内置DigitalServo和DAC [CD Digital Signal Processor with Built-in DigitalServo and DAC ]
分类和应用: 数字信号处理器
文件页数/大小: 134 页 / 942 K
品牌: ETC [ ETC ]
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CXD3018Q/R  
Signal  
Description  
PER0 to  
PER7  
RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.  
FOK  
GFS  
Focus OK  
High when the frame sync and the insertion protection timing match.  
GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight  
consecutive samples, a low signal is output.  
LOCK  
EMPH  
ALOCK  
High when the playback disc has emphasis.  
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is  
output. If GFS is low eight consecutive samples, a low signal is output.  
Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-3.)  
VF0 = LSB, VF7 = MSB.  
VF0 to VF7  
SPOA, B SPOA and SPOB pin inputs.  
WFCK  
SCOR  
GTOP  
RFCK  
Write frame clock output.  
High when either subcode sync S0 or S1 is detected.  
High when the sync protection window is open.  
Read frame clock output.  
XRAOF  
Low when the built-in 16K RAM exceeds the ±4 frame jitter margin.  
L0 to L7, Peak meter register output. L0 to L7 are the left-channel and R0 to R7 are the right-channel  
R0 to R7 peak data. L0 and R0 are LSB.  
C1F1  
C1F2  
C1 correction status  
No Error  
C2F1  
C2F2  
C2 correction status  
No Error  
0
1
1
0
0
1
0
1
1
0
0
1
Single Error Correction  
Irretrievable Error  
Single Error Correction  
Irretrievable Error  
Processing  
Command bit  
CPUSR = 1  
CPUSR = 0  
XLON pin is high.  
XLON pin is low.  
46 –  
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