UL62H256A
Write Cycle1: W-controlled
tcW
Address
Ai
th(A)
tsu(E)
E
tsu(A-WH)
tw(W)
W
tsu(A)
tsu(D)
Input Data Valid
ten(W)
th(D)
DQi
Input
tdis(W)
High-Z
DQi
Output
G
Write Cycle 2: E-controlled
tcW
Ai
E
Address Valid
tw(E)
tsu(A)
th(A)
tsu(W)
tsu(D)
W
th(D)
DQi
Input Data Valid
Input
tdis(W)
ten(E
)
DQi
High-Z
Output
tdis(G)
G
undefined
L- to H-level
H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to change design reserved.
May 07, 2004
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