Z8 Encore!® Motor Control Flash MCUs
Product Specification
54
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Execution of a Trap instruction
Illegal Instruction trap
System Exceptions
The Z8FMC16100 Series Flash MCU supports multiple system exceptions. System
exceptions are generated for the following events:
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Illegal Instruction trap
Watch-Dog Timer interrupt
Watch-Dog Timer RC oscillator failure
Primary oscillator failure
System exceptions, excluding the Watch-Dog Timer interrupt, are nonmaskable and there-
fore cannot be disabled by the interrupt controller (setting IRQEto 0 has no effect).
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 interrupts are
always higher priority than Level 2 interrupts. Level 2 interrupts are always higher priority
than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2, or Level 3),
priority is assigned as specified in Table 29.
Interrupt Assertion
When an interrupt request occurs, the corresponding bit in the Interrupt Request Register
is set. This bit is automatically cleared when the eZ8 CPU vectors to the Interrupt Service
Routine (ISR). Writing a 0 to the corresponding bit in the Interrupt Request Register also
clears the interrupt request.
If an interrupt is disabled, software can poll the appropriate interrupt request register bit
and clear the bit directly. The following style of coding to clear bits in the Interrupt Re-
quest registers is not recommended. All incoming interrupts that are received between
execution of the first LDX command and the last LDX command are lost.
Caution:
The following code segment is an example of a poor coding style that can result in lost
interrupt requests:
LDX r0, IRQ0
AND r0, MASK
Q0, r0
Interrupt Controller
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
