Z8FMC16100 Series Flash MCU
Product Specification
53
Architecture
Figure 6 illustrates a block diagram of the interrupt controller.
Port Interrupts
High
Priority
Vector
Priority
Internal Interrupts
Medium
Priority
Mix
Service Request
System Exceptions
Low
Priority
Figure 6. Interrupt Controller Block Diagram
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
•
Execution of an Enable Interrupt (EI) instruction
Execution of a Return from Interrupt (IRET) instruction
Writing a 1 to the IRQEbit in the Interrupt Control Register
Interrupts are globally disabled by any of the following actions:
•
•
•
•
Execution of a Disable Interrupt (DI) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQEbit in the Interrupt Control Register
Reset
PS024604-1005
P R E L I M I N A R Y
Architecture
ZILOG [ ZILOG, INC. ]
