Z8FMC16100 Series Flash MCU
Product Specification
51
Interrupt Controller
The interrupt controller on the Z8FMC16100 Series Flash MCU prioritizes the system
exceptions and interrupt requests from the on-chip peripherals and the GPIO port pins.
The features of the interrupt controller include the following:
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Multiple GPIO interrupts
Interrupts for on-chip peripherals
Nonmaskable system exceptions
Three levels of individually programmable interrupt priority
20 sources of interrupts for the interrupt controller, 9 of the sources can be configured
from GPIO pins
System exceptions (SEs) and interrupt requests (IRQs) allow peripheral devices to sus-
pend CPU operation in an orderly manner and force the CPU to start a service routine.
Interrupt service routines are involved with the exchange of data, status information, or
control information between the CPU and the interrupting peripheral. When the service
routine is completed, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt controller has no effect on operation. Refer to the eZ8 CPU User Manual
(UM0128) for more information regarding interrupt servicing by the eZ8 CPU. The eZ8
CPU User Manual is available for download at www.zilog.com.
Interrupt and System Exception Vector Listing
Table 29 lists the system exceptions and the interrupts in order of priority. Reset and sys-
tem exceptions always have priority over interrupts. The system exception and interrupt
vectors are stored with the most significant byte (MSB) at the even Program Memory
address and the least significant byte (LSB) at the following odd Program Memory
address.
Port interrupts are only available in those packages which support the associated port pins.
Note:
PS024604-1005
P R E L I M I N A R Y Interrupt and System Exception Vector Listing
ZILOG [ ZILOG, INC. ]
