Z8 Encore!® Motor Control Flash MCUs
Product Specification
254
BRKPC—Break when PC == OCDCNTR
If this bit is set to 1, then the OCDCNTR register is used as a hardware breakpoint. When
the program counter matches the value in the OCDCNTR register, DBGMODE is auto-
matically set to 1. If this bit is set, the OCDCNTR register does not count when the CPU is
running.
0 = OCDCNTR is setup as counter
1 = OCDCNTR generates hardware break when PC == OCDCNTR
BRKZRO—Break when OCDCNTR == 0000H
If this bit is set, then the OCD automatically sets the DBGMODE bit when the OCD-
CNTR register counts down to 0000H. If this bit is set, the OCDCNTR register is not reset
when the part leaves DEBUG Mode.
0 = OCD does not generate BRK when OCDCNTR decrements to 0000H
1 = OCD sets DBGMODE to 1 when OCDCNTR decrements to 0000H
Reserved—Must be 0.
RST—Reset
Setting this bit to 1 resets the device. The controller goes through a normal Power-On
Reset sequence with the exception that the On-Chip Debugger is not reset. This bit is auto-
matically cleared to 0 when the reset finishes.
0 = No effect.
1 = Reset the device.
OCD Status Register
The OCD Status Register, shown in Table 136, reports status information about the current
state of the debugger and the system. A more detailed description of each bit follows the
table.
Table 136. OCD Status Register (OCDSTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IDLE
HALT
RPEN
Reserved
0
0
0
0
R
R
R
R
IDLE—CPU idle
This bit is set if the part is in Debug mode (DBGMODE is 1) or if a BRK instruction has
occurred since the last time OCDCTL was written. This can be used to determine if the
CPU is running or if it is idle.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
On-Chip Debugger
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
