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Z8FMC04100QKSG 参数 Datasheet PDF下载

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型号: Z8FMC04100QKSG
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采-R电机控制闪存MCU [Z8 Encore-R Motor Control Flash MCUs]
分类和应用: 闪存微控制器和处理器外围集成电路电机时钟
文件页数/大小: 402 页 / 4558 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8FMC16100 Series Flash MCU  
Product Specification  
253  
A reset and stop function can be achieved by writing 81Hto this register. A reset and go  
function is achieved by writing 41Hto this register. If the device is in DEBUG mode, a run  
function is implemented by writing 40hto this register.  
A more detailed description of each bit follows the table.  
Table 135. OCD Control Register (OCDCTL)  
BITS  
FIELD  
RESET  
R/W  
7
6
5
4
3
2
1
0
RST  
0
BRKPC  
BRKZRO Reserved  
DBGMODE BRKEN DBGACK BRKLOOP  
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R
R/W  
R/W  
R/W  
R/W  
DBGMODE—Debug Mode  
Setting this bit to 1 causes the device to enter Debug mode. When in DEBUG mode, the  
eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to resume  
execution. This bit is automatically set when a BRK instruction is decoded and Break-  
points are enabled.  
0 = The device is running (operating in NORMAL mode).  
1 = The device is in DEBUG mode.  
BRKEN—Breakpoint Enable  
This bit controls the behavior of the BRK instruction (opcode 00H). By default, Break-  
points are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a  
BRK instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit.  
0 = BRK instruction is disabled.  
1 = BRK instruction is enabled.  
DBGACK—Debug Acknowledge  
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends  
a Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. This bit  
automatically clears itself when an acknowledge character is sent.  
0 = Debug Acknowledge is disabled.  
1 = Debug Acknowledge is enabled.  
BRKLOOP—Breakpoint Loop  
This bit determines what action the OCD takes when a BRK instruction is decoded and  
breakpoints are enabled (BRKEN is 1). If this bit is 0, the DBGMODE bit is automatically  
set to 1 and the OCD enters DEBUG mode. If BRKLOOP is set to 1, the eZ8 CPU loops  
on the BRK instruction.  
0 = BRK instruction sets DBGMODE to 1.  
1 = eZ8 CPU loops on BRK instruction.  
PS024604-1005  
P R E L I M I N A R Y  
OCD Control Register  
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