Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
179
SPI Master Mode Timing
Figure 96 and Table 110 provide timing information for SPI Master mode pins. Timing is
shown with SCK rising edge used to source MOSI output data, SCK falling edge used to
sample MISO input data. Timing on the SS output pin(s) is controlled by software.
SCK
T1
MOSI
(Output)
Output Data
T2
T3
MISO
Input Data
(Input)
Figure 96. SPI Master Mode Timing
Table 110. SPI Master Mode Timing
Delay (ns)
Parameter Abbreviation
Minimum Maximum
T1
T2
T3
SCK Rise to MOSI output Valid Delay
-5
20
0
+5
MISO input to SCK (receive edge) Setup Time
MISO input to SCK (receive edge) Hold Time
PS017610-0404
Electrical Characteristics