Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
178
On-Chip Debugger Timing
Figure 95 and Table 109 provide timing information for DBG pins. The timing specifica-
tions presume a rise and fall time on DBG of less than 4µs.
TCLK
XIN
T1
T2
T4
DBG
(Output)
Output Data
T3
DBG
(Input)
Input Data
Figure 95. On-Chip Debugger Timing
Table 109. On-Chip Debugger Timing
Delay (ns)
Minimum Maximum
Parameter Abbreviation
DBG
T1
T2
T3
T4
XIN Rise to DBG Valid Delay
–
2
15
–
XIN Rise to DBG Output Hold Time
DBG to XIN Rise Input Setup Time
DBG to XIN Rise Input Hold Time
DBG frequency
10
5
–
–
System
Clock / 4
PS017610-0404
Electrical Characteristics