Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
131
DMA Status Register
The DMA Status register indicates the DMA channel that generated the interrupt and the
ADC Analog Input that is currently undergoing conversion. Reads from this register reset
the Interrupt Request Indicator bits (IRQA, IRQ1, and IRQ0) to 0. Therefore, software
interrupt service routines that read this register must process all three interrupt sources
from the DMA.
Table 79. DMA_ADC Status Register (DMAA_STAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
CADC[3:0]
Reserved
IRQA
IRQ1
IRQ0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
FBFH
ADDR
CADC[3:0]—Current ADC Analog Input
This field identifies the Analog Input that the ADC is currently converting.
Reserved
This bit is reserved and must be 0.
IRQA—DMA_ADC Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA_ADC is not the source of the interrupt from the DMA Controller.
1 = DMA_ADC completed transfer of data from the last ADC Analog Input and generated
an interrupt.
IRQ1—DMA1 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA1 is not the source of the interrupt from the DMA Controller.
1 = DMA1 completed transfer of data to/from the End Address and generated an interrupt.
IRQ0—DMA0 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA0 is not the source of the interrupt from the DMA Controller.
1 = DMA0 completed transfer of data to/from the End Address and generated an interrupt.
PS017610-0404
Direct Memory Access Controller
ZILOG [ ZILOG, INC. ]
