Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
128
Table 74. DMAx Start/Current Address Low Byte Register (DMAxSTART)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DMA_START
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FB3H, FHBH
ADDR
DMA_START—DMAx Start/Current Address Low
These bits, with the four lower bits of the DMAx_H register, form the 12-bit Start/Current
address. The full 12-bit address is given by {DMA_START_H[3:0], DMA_START[7:0]}.
DMAx End Address Low Byte Register
The DMAx End Address Low Byte register, in conjunction with the DMAx_H register,
forms a 12-bit End Address.
Table 75. DMAx End Address Low Byte Register (DMAxEND)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DMA_END
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FB4H, FBCH
ADDR
DMA_END—DMAx End Address Low
These bits, with the four upper bits of the DMAx_H register, form a 12-bit address. This
address is the ending location of the DMAx transfer. The full 12-bit address is given by
{DMA_END_H[3:0], DMA_END[7:0]}.
DMA_ADC Address Register
The DMA_ADC Address register points to a block of the Register File to store ADC con-
version values as illustrated in Table 76. This register contains the seven most-significant
bits of the 12-bit Register File addresses. The five least-significant bits are calculated from
the ADC Analog Input number (5-bit base address is equal to twice the ADC Analog Input
number). The 10-bit ADC conversion data is stored as two bytes with the most significant
byte of the ADC data stored at the even numbered Register File address.
PS017610-0404
Direct Memory Access Controller
ZILOG [ ZILOG, INC. ]
