Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
84
6. Write to the UART Control 0 register to:
–
–
Set the receive enable bit (REN) to enable the UART for data reception
Enable parity, if desired, and select either even or odd parity.
The UART and DMA are now configured for data reception and automatic data transfer to
the Register File. When a valid data byte is received by the UART the following occurs:
7. The UART notifies the DMA Controller that a data byte is available in the UART
Receive Data register.
8. The DMA Controller requests control of the system bus from the eZ8 CPU.
9. The eZ8 CPU acknowledges the bus request.
10. The DMA Controller transfers the data from the UART Receive Data register to
another location in RAM and then return bus control back to the eZ8 CPU.
The UART and DMA can continue to transfer incoming data bytes without eZ8 CPU
intervention. When a UART error is detected, the UART Receiver interrupt is generated.
The associated interrupt service routine (ISR) should perform the following:
11. Check the UART Status 0 register to determine the source of the UART error or break
condition and then respond appropriately.
Multiprocessor (9-bit) mode
The UART has a Multiprocessor mode that uses an extra (9th) bit for selective communi-
cation when a number of processors share a common UART bus. In Multiprocessor (9-bit)
mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is transmitted immedi-
ately following the 8-bits of data and immediately preceding the STOP bit(s) as illustrated
in Figure 70. The character format is:
Data Field
STOP Bit(s)
Idle State
of Line
lsb
msb
Bit7
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
MP
1
2
Figure 70. UART Asynchronous Multiprocessor (9-bit) Mode Data Format
In Multiprocessor (9-bit) mode, parity is not an option as the Parity bit location (9th bit)
becomes the Multiprocessor control bit. The UART Control 1 and Status 1 registers pro-
vide multiprocessor (9-bit) mode control and status information.
PS017610-0404
UART
ZILOG [ ZILOG, INC. ]
