欢迎访问ic37.com |
会员登录 免费注册
发布采购

Z8F1602AR020EC 参数 Datasheet PDF下载

Z8F1602AR020EC图片预览
型号: Z8F1602AR020EC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采微控制器与闪存和10位A / D转换器 [Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter]
分类和应用: 转换器闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 246 页 / 1767 K
品牌: ZILOG [ ZILOG, INC. ]
 浏览型号Z8F1602AR020EC的Datasheet PDF文件第169页浏览型号Z8F1602AR020EC的Datasheet PDF文件第170页浏览型号Z8F1602AR020EC的Datasheet PDF文件第171页浏览型号Z8F1602AR020EC的Datasheet PDF文件第172页浏览型号Z8F1602AR020EC的Datasheet PDF文件第174页浏览型号Z8F1602AR020EC的Datasheet PDF文件第175页浏览型号Z8F1602AR020EC的Datasheet PDF文件第176页浏览型号Z8F1602AR020EC的Datasheet PDF文件第177页  
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x  
Z8 Encore!®  
155  
If the OCD receives a Serial Break (nine or more continuous bits Low) the Auto-Baud  
Detector/Generator resets. The Auto-Baud Detector/Generator can then be reconfigured  
by sending 80H.  
OCD Serial Errors  
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:  
Serial Break (a minimum of nine continuous bits Low)  
Framing Error (received Stop bit is Low)  
Transmit Collision (OCD and host simultaneous transmission detected by the OCD)  
When the OCD detects one of these errors, it aborts any command currently in progress,  
transmits a four character long Serial Break back to the host, and resets the Auto-Baud  
Detector/Generator. A Framing Error or Transmit Collision may be caused by the host  
sending a Serial Break to the OCD. Because of the open-drain nature of the interface,  
returning a Serial Break break back to the host only extends the length of the Serial Break  
if the host releases the Serial Break early.  
The host should transmit a Serial Break on the DBG pin when first connecting to the  
Z8F640x family device or when recovering from an error. A Serial Break from the host  
resets the Auto-Baud Generator/Detector but does not reset the OCD Control register. A  
Serial Break leaves the Z8F640x family device in Debug mode if that is the current mode.  
The OCD is held in Reset until the end of the Serial Break when the DBG pin returns  
High. Because of the open-drain nature of the DBG pin, the host can send a Serial Break to  
the OCD even if the OCD is transmitting a character.  
Breakpoints  
Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the  
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are  
enabled, the OCD enters Debug mode and idles the eZ8 CPU. If Breakpoints are not  
enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP.  
Breakpoints in Flash Memory  
The BRK instruction is opcode 00H, which corresponds to the fully programmed state of a  
byte in Flash memory. To implement a Breakpoint, write 00Hto the desired address, over-  
writing the current instruction. To remove a Breakpoint, the corresponding page of Flash  
memory must be erased and reprogrammed with the original data.  
Watchpoints  
The On-Chip Debugger can set one Watchpoint to cause a Debug Break. The Watchpoint  
identifies a single Register File address. The Watchpoint can be set to break on reads and/  
or writes of the selected Register File address. Additionally, the Watchpoint can be config-  
ured to break only when a specific data value is read and/or written from the specified reg-  
PS017610-0404  
On-Chip Debugger