Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
154
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Power-on reset
Voltage Brownout reset
Asserting the RESET pin Low to initiate a Reset.
Driving the DBG pin Low while the Z8F640x family device is in Stop mode initiates a
System Reset.
OCD Data Format
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1.5 Stop bits
(Figure 89)
START
D0
D1
D2
D3
D4
D5
D6
D7
STOP
Figure 89. OCD Data Format
OCD Auto-Baud Detector/Generator
To run over a range of baud rates (data bits per second) with various system clock frequen-
cies, the On-Chip Debugger has an Auto-Baud Detector/Generator. After a reset, the OCD
is idle until it receives data. The OCD requires that the first character sent from the host is
the character 80H. The character 80Hhas eight continuous bits Low (one Start bit plus 7
data bits). The Auto-Baud Detector measures this period and sets the OCD Baud Rate
Generator accordingly.
The Auto-Baud Detector/Generator is clocked by the Z8F640x family device system
clock. The minimum baud rate is the system clock frequency divided by 512. For optimal
operation, the maximum recommended baud rate is the system clock frequency divided by
8. The theoretical maximum baud rate is the system clock frequency divided by 4. This
theoretical maximum is possible for low noise designs with clean signals. Table 92 lists
minimum and recommended maximum baud rates for sample crystal frequencies.
Table 92. OCD Baud-Rate Limits
System Clock Frequency Recommended Maximum Baud Rate
Minimum Baud Rate
(kbits/s)
(MHz)
(kbits/s)
20.0
1.0
2500
39.1
1.96
125.0
0.032768 (32KHz)
4.096
0.064
PS017610-0404
On-Chip Debugger
ZILOG [ ZILOG, INC. ]
