Z8 Encore! XP® F08xA Series
Product Specification
74
Table 52. Timer 0–1 PWM Low Byte Register (TxPWML)
BITS
7
6
5
4
3
2
1
0
PWML
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F05H, F0DH
ADDR
PWMH and PWML—Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOLbit in the Timer Control Register (TxCTL1) regis-
ter.
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in Capture or Capture/Compare modes.
Timer 0–1 Control Registers
Time 0–1 Control Register 0
The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1) deter-
mine the timer operating mode. It also includes a programmable PWM deadband delay,
two bits to configure timer interrupt definition, and a status bit to identify if the most
recent timer interrupt is caused by an input capture event.
Table 53. Timer 0–1 Control Register 0 (TxCTL0)
BITS
7
6
5
4
3
2
1
0
TMODEHI
TICONFIG
Reserved
PWMD
INPCAP
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F06H, F0EH
ADDR
TMODEHI—Timer Mode High Bit
This bit along with the TMODE field in TxCTL1 register determines the operating mode
of the timer. This is the most significant bit of the Timer mode selection value. See the
TxCTL1 register description on the next page for additional details.
TICONFIG—Timer Interrupt Configuration
This field configures timer interrupt definition.
PS024705-0405
P R E L I M I N A R Y
Timers
ZILOG [ ZILOG, INC. ]
