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Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® F08xA Seriess  
Product Specification  
89  
Receiving Data using the Interrupt-Driven Method  
The UART Receiver interrupt indicates the availability of new data (as well as error condi-  
tions). Follow these steps to configure the UART receiver for interrupt-driven operation:  
1. Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud  
rate.  
2. Enable the UART pin functions by configuring the associated GPIO Port pins for  
alternate function operation.  
3. Execute a DI instruction to disable interrupts.  
4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set  
the acceptable priority.  
5. Clear the UART Receiver interrupt in the applicable Interrupt Request register.  
6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode  
functions, if appropriate.  
Set the Multiprocessor Mode Select (MPEN) to Enable MULTIPROCESSOR  
mode.  
Set the Multiprocessor Mode Bits, MPMD[1:0],to select the acceptable address  
matching scheme.  
Configure the UART to interrupt on received data and errors or errors only  
(interrupt on errors only is unlikely to be useful for Z8 Encore!® devices without a  
DMA block)  
7. Write the device address to the Address Compare Register (automatic  
MULTIPROCESSOR modes only).  
8. Write to the UART Control 0 register to:  
Set the receive enable bit (REN) to enable the UART for data reception  
Enable parity, if appropriate and if multiprocessor mode is not enabled, and select  
either even or odd parity.  
9. Execute an EI instruction to enable interrupts.  
The UART is now configured for interrupt-driven data reception. When the UART  
Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the  
following:  
1. Checks the UART Status 0 register to determine the source of the interrupt - error,  
break, or received data.  
2. Reads the data from the UART Receive Data register if the interrupt was because of  
data available. If operating in MULTIPROCESSOR (9-bit) mode, further actions may  
be required depending on the MULTIPROCESSOR mode bits MPMD[1:0].  
3. Clears the UART Receiver interrupt in the applicable Interrupt Request register.  
PS024705-0405  
P R E L I M I N A R Y  
UART